1. Technical Field
The invention relates generally to self-timed circuits, and more specifically, to self-timed circuits that detect the timing margin of critical signal paths in a clocked logic system.
2. Background Art
In a computer system, or in any other clocked logic system, the overall performance of the system is largely determined by the frequency of the system's clock signal. As the frequency, and thus the speed of the clock signal increases, the time required to execute system applications decreases. The speed of the system clock signal is limited, though, by the slowest components and/or chips that may be contained in the system, each component having a certain maximum speed at which it can safely operate. Thus, the clock signal frequency is generally determined by the worse case speed of the slowest possible components to ensure that the system will operate over the entire range of temperature and power supply. If the speed of a component barely falls short of one particular speed (e.g., 150 MHz), the whole system must be placed at the next lower speed (e.g., 133 MHz), which would be detrimental to the performance of the system.
To overcome the problem of limiting a system to the worse case speed of its components, self-timed circuits were used in clocked systems to dynamically change the speed of the clock. U.S. Pat. No. 5,451,892, "Clock Control Technique and System for a Microprocessor including a Thermal Sensor," issued September 1995 to Bailey discloses a circuit that monitors the temperature of the system and when certain thresholds are met, will change the frequency of the clock signal. Although the temperature is important in determining the speed at which the system component's may operate, other factors, such as voltage, may also be involved that would cancel out the effects of the temperature factor, thus causing the frequency of the clock to be incorrectly determined.
Other examples of clocked systems that are dynamically self-timed include: U.S. Pat. No. 5,455,521, "Self-Timed Interconnect Speed-Up Circuit," issued October 1995 to Dobbelaere; U.S. Pat. No. 5,329,176, "Self-Timed Clocking System and Method for Self-Timed Dynamic Logic Circuits," issued July 1994 to Miller, Jr. et al.; and U.S. Pat. No. 5,434,520, "Clocking Systems and Methods for Pipelined Self-Timed Dynamic Logic Circuits," issued Jul. 18, 1995 to Yetter et al. The above-mentioned patents disclose self-timed systems, but they do not take into account all the factors that can slow down, or speed up a clocked logic system.
Accordingly, a need has developed in the art for a self-timed circuit for a clocked logic system with dynamic sensing that will adjust the speed of a clock according to the timing margin of the components in a particular system, thus permitting the system to operate at the fastest speed the components and environment allow.